#Time punch clock calculator how to#
#Time punch clock calculator series#

Again, traces on top, uninterrupted ground plane right under them, along the entire length of the pairs.

Let’s aim for on-point 85 ohm differential impedance today – a great target wherever you can afford it. After replacing the default parameters there with the 4-layer impedance controlled process ones – clearance, minimum trace width, via size and such, – we get some pretty lovely parameters that we can drop down to if there’s ever a tight spot, and an ability to do reasonably dense component placement. I went by parameters on the JLCPCB stackup page, and took via parameters from the ordering page – you can put these parameters into the “File => Board Setup” window, in the “Net Classes” tab. Initially, I’m choosing the 7628 stackup variant here – the main difference between stackups here is the prepreg thickness and the dielectric constant, which impacts minimum possible diffpair thickness and spacing. According to the design rules, I can go down to 3.5 mil (0.09 mm) traces and spacings, as opposed to the usual 6 mil (0.16 mm) traces I’m used to when doing generic 2-layer boards. This time, I’m going with a 4-layer 0.8 mm stackup – otherwise the board won’t fit into an M.2 socket.

#Time punch clock calculator how to#

I, sadly, don’t yet understand how to calculate differential impedance for signal layers sandwiched between two ground planes, which is to say – if there’s any commenters willing to share this knowledge, I’d appreciate your input tremendously! For now, I don’t see that there’d be a tangible benefit to such an arrangement, anyway.

Our setup is, once again, having signals on outer layers, referenced to the ground layer right below them.

We’ve talked about differential pair calculations before in one of the PCIe articles, and there was a demo video too! That said, let’s repeat the calculations on this one – I’ll show how to get from “PCB fab website information” to “proper width and clearance diffpairs”, with a few fun shortcuts. For that, I took the footprints from ‘s wonderful project, called “Effect of moon phase on tombstoning” – with such a name, these footprints have got to be good. I only remembered this after having finished routing all the diffpairs, and, after a bit of deliberation, I decided that this is my chance to try 0201 capacitors. We need three capacitor pairs here – on TX of the PCIe switch uplink, and two pairs on TX side of the switch – again, naming is host-side.

#Time punch clock calculator series#

While initially routing this board, I absolutely forgot about one more important thing for PCIe – series capacitors on every data pair, on the host TX side of the link.

To sum up, we only need to flip the names on the link coming to the PCIe switch, since the PCIe switch acts as a device on the card the two links from the switch go to the E-key socket, and for that socket’s purposes, the PCIe switch acts as a host. As the diagram demonstrates, we connect the socket’s TX to chip’s RX and vice-versa if we ever get confused, the laptop schematic is there to help us make things clear. Connectors will use host-side naming, and vice-versa. PCIe needs TX pairs connected to RX on another end, like UART – and this is non-negotiable. By now, the schematic is done, the component placement has been figured out, and we only need to route the differential pairs – should be simple, right? Buckle up. We’ve started designing a PCIe card last week, an adapter from M.2 E-key to E-key, that adds an extra link to the E-key slot it carries – useful for fully utilizing a few rare but fancy E-key cards.